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- Regular price
- £10.99 inc VAT
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The ASRock TPM-SPI is a hardware security module for PC builders and system upgraders whose compatible motherboard has an SPI TPM header. It provides a discrete TPM 2.0 option for systems that need hardware-based storage for security keys and related data.
Using the SPI interface, the module is designed to support platform security functions, including secure storage of keys, digital certificates, passwords and data. It complies with TPM Main Specification Family 2.0, Level 00, Revision 01.16. ASRock also states that it meets qualification criteria for Intel TXT, Microsoft Windows and Google Chromebook platforms. Its low typical standby power consumption of 110µA is suited to systems where reducing idle power matters.
Key features
- TPM 2.0 functionality for supported systems
- SPI interface for connection to a compatible motherboard header
- 13-pin connector for the specified TPM-SPI connection
- Supports 24 PCRs using SHA-1 or SHA-256
- Includes an RNG that follows NIST SP800-90A
- Provides 7206 Byte of free NV memory
- Low typical standby power consumption of 110µA
Compatibility
ASRock specifies support on X570 and newer platform motherboards and lists Windows 10 with a UEFI OS as the system requirement. Check the motherboard manual for an SPI TPM header and confirm the connector and pin layout before buying; a different TPM header or interface may not fit or work. Good to know: this is an SPI module with a 13-pin connector, so motherboard compatibility depends on having the matching SPI TPM header.
In the box
- ASRock TPM-SPI
Specifications
| Specification | Detail |
|---|---|
| Product type | TPM 2.0 module |
| Part number | TPM-SPI |
| Interface | SPI |
| Connector | 13 pin |
| Supported platform | X570 and newer platform motherboards |
| System requirements | Windows® 10, UEFI OS |
| Standby power consumption | typ. 110µA |
For a compatible ASRock system, the TPM-SPI adds a dedicated TPM 2.0 module in a compact format, with a standards-based feature set for platform security and a clearly specified SPI connection.
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